1. Field of the Invention
The present invention relates to a read only memory for storing bit data in accordance with the presence or absence of a transistor at the intersection of a bit line and a word line corresponding to each of the addresses of bit data to be stored. More particularly, the invention relates to a read only memory capable of preventing logic state malfunction by eliminating the unpredictable logic states of bit lines.
2. Prior Art
While random access memories (RAM's) are generally volatile when it comes to retaining their contents, read only memories (ROM's) are non-volatile in terms of data retention. The so-called mask ROM is one of such ROM's. The memory contents of this ROM are permanently built into the device during its integrated circuit manufacture. For example, a suitable mask is used during the manufacturing stage to fix the state of a transistor presence or absence (on- or off-state) at the intersection of a bit line and a word line representing each of the addresses of bit data to be stored. The bit data thus written permanently are highly reliable in data status constancy compared with the programmable ROM (PROM), another type in the ROM category.
FIG. 3 is a circuit diagram of a first prior art example of the conventional CMOS (complementary metal oxide semiconductor) mask ROM. FIG. 3 emphasizes that portion of the CMOS mask ROM which stores bit data.
In FIG. 3, reference characters WL0 through WL3 stand for word lines and BL0 and BL1 for bit lines. Reference characters PCHG designate a precharge line. This line goes Low for a predetermined period for precharging before any one of the word lines WL0 through WL3 is brought High for the applicable bit data to be read out.
The mask ROM is designed to minimize the number of transistors so as to increase the degree of integration. For that purpose, bit data are generally written by simply establishing the presence or absence of a transistor (also called a memory cell transistor hereinafter) at the intersection of a bit line and a word line representing each of the addresses of the bit data to be stored. In other words, bit data are not written by selecting either a transistor connected to the power supply or a transistor connected to ground.
In the mask ROM of the above construction, precharging is performed prior to the access stage for data read operations. The precharging action involves charging the bit lines beforehand up to the power supply level. During read access, the bit line with its memory cell transistor intersecting an enabled word line is discharged to reach ground level. At this point, the bit lines with no memory cell transistor intersecting the enabled word line remain at their power supply level.
In FIG. 3, the leftmost positions of the bit lines BL0 and BL1 are connected respectively to the sources of P-channel MOS transistors TP0 and TP1 with their drains connected to the power supply VCC. The bit data are written by establishing the presence or absence of N-channel MOS transistors TN1 and TN2 which are the memory cell transistors.
When any one of the word lines WL0 through WL3 is brought High, the states of the bit lines BL0 and BL1 are read out as bit data respectively to bit data lines BD0 and BD1 by inverters G1 and G2 acting as sense amplifiers.
There are three representative methods for establishing the presence or absence of memory cell transistors at the intersections between bit lines and word lines and for permanently fixing the bit data states thus determined. One such method is a diffusion layer code mask method that involves determining the presence or absence of a diffusion layer region that corresponds to the source and drain of each memory cell transistor. Another method is an ion implantation code mask method that varies the threshold value of a given memory cell transistor by means of ion implantation, thereby switching the on- and off-states of that transistor. The other method is a contact code mask method that uses a contact mask to switch the presence and absence of connection contacts between memory cell transistors on the one hand, and bit or word lines on the other.
FIG. 4 is a diagram showing some bit data written in the first prior art example of the mask ROM. In FIG. 4, each of word addresses "0" through "3" corresponds to the High state of any one of the word lines WL0 through WL3 in the first prior art example. Bit addresses "0", "1" . . . in FIG. 4 correspond to the bit lines BL0 and BL1 in FIG. 3.
The word line WL0 and the bit line BL0, connected to the N-channel MOS transistor TN1 (memory cell transistor) in the first prior art example, correspond respectively to word address "0" and bit address "0" of FIG. 4. Bit date of the two addresses represent "1" (High state). The word line WL3 and the bit line BL0, connected to the N-channel MOS transistor TN2 (memory cell transistor) in the first prior art example, correspond respectively to word address "3" and bit address "0" of the FIG. 4. Bit data of the two addresses also represent "1" (High state). All other bit data in the diagram shown in FIG. 4 are "0" (Low states).
FIG. 5 is a circuit diagram of a second prior art example of the prior art CMOS mask ROM. In FIG. 5, reference characters TP0, TP1, TN1, TN2, G0, G1, WL0 through WL3, BL0, BL1, BD0, BD1, PCHG, VCC and GND designate the same parts as those in FIG. 3. The bit data written in the second prior art example are also the same as those shown in FIG. 4.
In the second prior art example, bringing the outputs of the inverters G0 and G1 Low turns on the P-channel MOS transistors TP10 and TP11 that correspond respectively to the inverters. The inputs to the inverters G0 and G1 are held High. The data states established in the second prior art example are the same as those in FIG. 4.
One disadvantage of the first prior art example is that, while "0" (Low state) is being read out, the logic state of the applicable bit line tends to float, i.e., connected neither to the power supply VCC nor to ground GND. the unstable floating state can cause the bit data "0" being read out to turn itself into "1" (High state). This is because the logic state of the bit line corresponding to the Low state under reading relies solely on the electric charge from the precharging operation.
FIG. 6 is a timing chart in effect when bit data are read from the first prior art example. In FIG. 6, reference characters PCHG indicate the timing of the logic state of the precharge line represented by the same reference characters (PCHG) in FIG. 3. Reference characters WL of FIG. 6 indicate the timing of the logic state of any one of the word lines WL0 through WL3 in FIG. 3. Reference characters BL(L) stand for the timing of the logic state in effect when the Low state of the bit line BL0 or BL1 in FIG. 3 is read out. Reference characters BL(H) represent the logic state in effect when the High state of the bit line BL0 or BL1 in FIG. 3 is read out.
In FIG. 6, a time t.sub.1 is preceded by a precharge period wherein the logic state PCHG takes the Low state. The time t.sub.1 is followed by an access state period wherein the logic state PCHG is the High state. At a time t.sub.2, the logic state WL is the High state.
When a bit line is brought Low and a High-state bit data is read out therefrom, the logic state BL(L) becomes Low at a time t.sub.3 in response to the logic state WL being High. When a bit line is brought High and a Low-state bit data is read out therefrom, the logic state BL(H) remains High thanks to the electric charge from the precharge period even as the logic state WL goes High after the access state period has started. However, because the High state of BL(H) relies on the amount of electric charge, the voltage drops following the discharge.
As shown in FIG. 6, the voltage level of BL(H) drops below a threshold value Vsw at a time t.sub.4. This causes the logic state of the applicable bit line to go Low. That is, the Low-state output of the inverter G0 or G1 in FIG. 3 can become High. This is one or the disadvantage of the first prior art example.
One disadvantage of the second prior art example is as follows: After a given bit line is brought High by a precharge operation, while "1" (High state) is being read out the bit line goes Low and a High-state bit data is read out therefrom. In this case, a through current flows across the P-channel MOS transistor for holding the logic state of bit line to the memory cell transistor (N-channel MOS transistor) that is turned on upon read-out. As a result, power dissipation is promoted.
For example, in FIG. 5, a precharging operation brings the outputs of the inverters G0 and G1 Low, followed by P-channel MOS transistors TP10 and TP11 being turned on. Thereafter, the bit data corresponding to the word line WL0 and the bit line BL0 are read out. This turns on both the P-channel MOS transistor TP10 and the N-channel MOS transistor TN1 and keeps them on until the output of the inverter G0 becomes High. A through current flows across these two transistors from the power supply VCC to the ground GND. Power consumption is increased in this manner.